1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for forming a pad polycrystalline silicon layer pattern at a presumed region of a contact plug for a high integration device, and forming the contact plug according to a selective epitaxial growth (SEG) method using the pad polycrystalline silicon layer pattern as a seed.
2. Description of the Background Art
Recently, the high integration of a semiconductor device has been remarkably influenced by the development of techniques for forming a fine pattern. In a method for fabricating the semiconductor device, it is essential to miniaturize a photoresist film pattern used as a mask in an etching or ion implantation process.
Resolution (R) of the photoresist film pattern is proportional to a light source wavelength (xcex) and a process variable (k) of a micro exposure device, and inversely proportional to a numerical aperture (NA) of the exposure device, and is given by:
R=k*xcex/NA 
Here, in order to improve optical resolution of the micro exposure device, the wavelength of the light source is decreased. For example, resolution of the G-line and i-line micro exposure devices, having wavelengths of 436 nm and 365 nm, respectively is limited to about 0.7 xcexcm and 0.5 xcexcm, respectively. Accordingly, the exposure device using a deep ultraviolet (DUV) light having a small wavelength, for example, a KrF laser of 248 nm or an ArF laser of 193 nm, is employed to form a fine pattern less than 0.5 xcexcm. In addition, in order to improve the resolution, a method for using a phase shift mask as a photo mask has been suggested. A contrast enhancement layer (CEL) method for forming a thin film on a wafer has been suggested for enhancing an image contrast. A tri layer resist (TLR) method has been suggested for positioning an intermediate layer, such as a spin on glass (SOG) film, between two photoresist films. And a silylation method has been suggested for selectively implanting a silicon into an upper portion of a photoresist film.
According to the high integration of the semiconductor device, the size of a contact hole, which connects the upper and lower conductive interconnections, and the space between the contact hole and an adjacent interconnection are decreased, and an aspect ratio which is the ratio of diameter and depth in the contact hole is increased.
The high integration semiconductor device having multi-layer conductive interconnections requires precise alignment of masks in a contact formation process, thereby reducing a process margin.
In order to maintain a space between the contact holes, masks are formed in consideration of: misalignment tolerance in a mask alignment, lens distortion in an exposure process, critical dimension variations in mask formation and photoetching processes, and mask registration between masks.
In addition, there has been taught a self aligned contact (SAC) method for forming a contact hole according to a self alignment method to overcome a disadvantage of a lithography process.
The SAC method uses a polycrystalline silicon layer, a nitride film or an oxide nitride film as an etching barrier film. In general, the nitride film is employed as the etching barrier film.
Although not illustrated, the conventional SAC method for fabricating the semiconductor device will now be described.
Firstly, a substructure consisting of, for example, a device isolating insulating film, a gate insulating film and a metal-oxide semiconductor field effect transistor (MOSFET) having a gate electrode overlapped with a gate insulating film and a mask insulating film pattern, and source/drain regions are formed on a semiconductor substrate. An etching barrier film and an interlayer insulating film consisting of an oxide film are sequentially formed over the whole surface of the structure.
Thereafter, a photoresist film pattern exposing a presumed region for a storage electrode contact or bit line contact on the semiconductor substrate is formed on the upper side of the interlayer insulating film.
The interlayer insulating film exposed by the photoresist film pattern is dry-etched to expose the etching barrier film. Then, a contact hole is formed by etching the etching barrier film.
In the conventional SAC method for fabricating the semiconductor device, the bit line contact and the storage electrode contact are formed according to the SAC method using the nitride film or oxide nitride film. In this case, the contact is formed in a hall or T type.
In the case of the hall type contact, the overlap precision of the lithography process has a limit and the contact hole has a sloped section in the etching process of a planarization film. Thus, it is difficult to obtain a contact region. In order to overcome the disadvantages of the hall type contact, the hall type contact is transformed into the T type contact.
However, to form the T type contact a chemical mechanical polishing (CMP) process is performed several times, thereby increasing fabrication costs. In addition, the CMP process includes a complicated and difficult process for isolating a contact plug, so that it cannot achieve mass-production. Furthermore, a yield of the device is reduced.
Accordingly, there has been suggested a method for forming the contact plug according to a selective epitaxial growth (SEG) method.
However, when an insulating film spacer is formed at the sidewalls of the gate electrode, the semiconductor substrate is damaged, thereby restricting the selective epitaxial growth. That is, a growth rate of a selective epitaxial growth film has a limit. Thus, it is difficult to form the contact plug having a free height.
When the planarization film is etched to form the succeeding bit line contact or storage electrode contact, the contact plug may damage the device isolating film, thereby causing gate induced drain leakage. Accordingly, a property of the device is deteriorated, and simultaneously a yield thereof is reduced.
Therefore, there is a need to provide a method for fabricating a semiconductor device which can prevent gate induced drain leakage by forming a MOSFET, forming a pad polycrystalline silicon layer pattern at a presumed region of a contact plug, and then forming the contact plug according to a selective epitaxial growth (SEG) method using the pad polycrystalline silicon layer pattern as a seed, and which can improve a contact resistance property and a device operation property by reducing a contact junction leakage current.
Accordingly, the present invention provides a method for fabricating a semiconductor device, the method including: forming an isolating film for defining an active region on a semiconductor substrate; forming a gate insulating film over the whole surface of the structure; forming on the gate insulating film a gate electrode where a mask insulating film pattern is stacked; forming an insulating film spacer at the sidewalls of the gate electrode and the mask insulating film pattern; forming source/drain regions at the both sides of the insulating film spacer on the semiconductor substrate; forming a pad polycrystalline silicon layer pattern at a presumed region for a bit line contact and a storage electrode contact on the semiconductor substrate, and at the sidewalls of the insulating film spacer; forming a contact plug according to a selective epitaxial growth method using the pad polycrystalline silicon layer pattern as a seed; forming a planarization film over the whole surface of the structure; and forming a contact hole by etching the planarization film by using a contact mask for exposing the contact plug as an etching mask.